 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| 1 of 42 112299 note: some revisions of this device may incorporate deviations from published specifications known as errata. multiple revisions of any device may be simultaneously available through various sales channels. for inf ormation about device errata, click here: http://www.maxim - ic.com/errata . features 80c32 - compatible - 8051 pin and instruction set compatible - four 8 - bit i/o ports - three 16 - bit timer/counters - 256 bytes scratchpad ram - addresses 64 kb rom and 64 kb ram high - speed architecture - 4 clocks/machine cycle (8032=12) - dc to 33 m hz (ds80c320) - dc to 18 mhz (ds80c323) - single - cycle instruction in 121 ns - uses less power for equivalent work - dual data pointer - optional variable length movx to access fast/slow ram/peripherals high integration controller includes: - power - fail reset - programm able watchdog timer - early - warning power - fail interrupt two full - duplex hardware serial ports 13 total interrupt sources with six external available in 40 - pin dip, 44 - pin plcc and tqfp pin assignment ds80c320/ds80c323 high - speed/low - power micro www.m axim - ic.com
ds80c320/ds80c323 2 of 42 description the ds80c320/ds80c323 is a fast 80c31/80 c32 - compatible microcontroller. wasted clock and memory cycles have been removed using a redesigned processor core. as a result, every 8051 instruction is executed between 1.5 and 3 times faster than the original for the same crystal speed. typical applica tions will see a speed improvement of 2.5 times using the same code and same crystal. the ds80c320 offers a maximum crystal rate of 33 mhz, resulting in apparent execution speeds of 82.5 mhz (approximately 2.5x). the ds80c320/ds80c323 is pin - compatible wi th all three packages of the standard 80c32 and offers the same timer/counters, serial port, and i/o ports. in short, the device is extremely familiar to 8051 users but provides the speed of a 16 - bit processor. the ds80c320 provides several extras in addi tion to greater speed. these include a second full hardware serial port, seven additional interrupts, programmable watchdog timer, power - fail interrupt and reset. the device also provides dual data pointers (dptrs) to speed block data memory moves. it can also adjust the speed of off - chip data memory access to between two and nine machine cycles for flexibility in selecting memory and peripherals. the ds80c320 operating voltage ranges from 4.25v to 5.5v, making it ideal as a high - performance upgrade to exi sting 5v systems. for applications in which power consumption is critical, the ds80c323 offers the same feature set as the ds80c320, but with 2.7v to 5.5v operation. ordering information part number package max clock speed temperature range ds80c320 - mcg 40 - pin plastic dip 25 mhz 0c to +70c ds80c320 - qcg 44 - pin plcc 25 mhz 0c to +70c ds80c320 - ecg 44 - pin tqfp 25 mhz 0c to +70c ds80c320 - mng 40 - pin plastic dip 25 mhz - 40c to +85c ds80c320 - qng 44 - pin plcc 25 mhz - 40c to +85c ds80c320 - eng 44 - pin t qfp 25 mhz - 40c to +85c ds80c320 - mcl 40 - pin plastic dip 33 mhz 0c to +70c ds80c320 - qcl 44 - pin plcc 33 mhz 0c to +70c ds80c320 - ecl 44 - pin tqfp 33 mhz 0c to +70c ds80c320 - mnl 40 - pin plastic dip 33 mhz - 40c to +85c ds80c320 - qnl 44 - pin plcc 33 m hz - 40c to +85c ds80c320 - enl 44 - pin tqfp 33 mhz - 40c to +85c ds80c323 - mcd 40 - pin plastic dip 18 mhz 0c to +70c ds80c323 - qcd 44 - pin plcc 18 mhz 0c to +70c ds80c323 - ecd 44 - pin tqfp 18 mhz 0c to +70c ds80c320/ds80c323 3 of 42 ds80c320 block diagram figure 1 ds80c320/ds80c323 4 of 42 pin de scription table 1 dip plcc tqfp signal name description 40 44 38 v cc v cc - +5v. (+3v ds80c323) 20 22, 23 16, 17 gnd gnd - digital circuit ground. 9 10 4 rst rst - input . the rst input pin contains a schmitt voltage input to recognize external active hig h reset inputs. the pin also employs an internal pulldown resistor to allow for a combination of wired or external reset sources. an rc is not required for power - up, as the device provides this function internally. 18 19 20 21 14 15 xtal2 xtal1 xtal1, xta l2 - the crystal oscillator pins xtal1 and xtal2 provide support for parallel resonant, at cut crystals. xtal1 acts also as an input in the event that an external clock source is used in place of a crystal. xtal2 serves as the output of the crystal amplifi er. 29 32 26 psen psen - output . the program store enable output. this signal is commonly connected to external rom memory as a chip enable. psen will provide an active low pulse width of 2.25 xtal 1 cycles with a period of four xtal1 cycles. psen is driven high when data memory (ram) is being accessed through the bus and during a reset condition. 30 33 27 ale ale ? output . the address latch enable output functions as a clock to l atch the external address lsb from the multiplexed address/data bus. this signal is commonly connected to the latch enable of an external 373 family transparent latch. ale has a pulse width of 1.5 xtal1 cycles and a period of four xtal1 cycles. ale is forc ed high when the device is in a reset condition. 39 38 37 36 35 34 33 32 43 42 41 40 39 38 37 36 37 36 35 34 33 32 31 30 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 ad0 - 7 (port 0) - i/o. port 0 is the multiplexed address/data bus. during the time when ale is high, th e lsb of a memory address is presented. when ale falls, the port transitions to a bi - directional data bus. this bus is used to read external rom and read/write external ram memory or peripherals. the port 0 has no true port latch and can not be written d irectly by software. the reset condition of port 0 is high. no pullup resistors are needed. 1 - 8 2 - 9 40 - 44 1 - 3 p1.0 - p1.7 port 1 - i/o . port 1 functions as both an 8 - bit bi - directional i/o port and an alternate functional interface for timer 2 i/o, new ext ernal interrupts, and new serial port 1. the reset condition of port 1 is with all bits at a logic 1. in this state, a weak pullup holds the port high. this condition also serves as an input mode, since any external circuit that writes to the port will ove rcome the weak pullup. when software writes a 0 to any port pin, the device will activate a strong pulldown that remains on until either a 1 is written or a reset occurs. writing a 1 after the port has been at 0 will cause a strong transition driver to tur n on, followed by a weaker sustaining pullup. once the momentary strong driver turns off, the port once again becomes the output high (and input) state. the alternate modes of port 1 are outlined as follows: port alternate function 1 2 40 p1.0 t2 ex ternal i/o for timer/counter 2 2 3 41 p1.1 t2ex timer/counter 2 capture/reload trigger 3 4 42 p1.2 rxd1 serial port 1 input 4 5 43 p1.3 txd1 serial port 1 output 5 6 44 p1.4 int2 external interrupt 2 (positive edge detect) 6 7 1 p1.5 int3 external interrupt 3 (negative edge detect) 7 8 2 p1.6 int4 external interrupt 4 (positive edge detect) 8 9 3 p1.7 int5 external interrupt 5 (negative edge detect) ds80c320/ds80c323 5 of 42 dip plcc tqfp signal name description 21 22 23 24 25 26 27 28 24 25 26 27 28 29 30 31 18 19 20 21 22 23 24 25 a8 (p2.0) a9 (p2.1) a10 (p2.2) a11 (p2.3) a12 (p2.4) a13 (p2.5) a14 (p2.6) a15 (p2.7) a15 - a8 (port 2) - output . port 2 serves as the msb for external addressing. p2.7 is a15 and p2.0 is a8. the devic e will automatically place the msb of an address on p2 for external rom and ram access. although port 2 can be accessed like an ordinary i/o port, the value stored on the port 2 latch will never be seen on the pins (due to memory access). therefore writing to port 2 in software is only useful for the instructions movx a, @ri or movx @ri, a. these instructions use the port 2 internal latch to supply the external address msb. in this case, the port 2 latch value will be supplied as the address information. 1 0 - 17 11, 13 - 19 5, 7 - 13 p3.0 - p3.7 port 3 - i/o. port 3 functions as both an 8 - bit bi - directional i/o port and an alternate functional interface for external interrupts, serial port 0, timer 0 & 1 inputs, rd and wr s trobes. the reset condition of port 3 is with all bits at a logic 1. in this state, a weak pullup holds the port high. this condition also serves as an input mode, since any external circuit that writes to the port will overcome the weak pullup. when softw are writes a 0 to any port pin, the device will activate a strong pulldown that remains on until either a 1 is written or a reset occurs. writing a 1 after the port has been at 0 will cause a strong transition driver to turn on, followed by a weaker susta ining pullup. once the momentary strong driver turns off, the port once again becomes both the output high and input state. the alternate modes of port 3 are outlined below: port alternate mode 10 11 5 p3.0 rxd0 serial port 0 input 11 13 7 p3.1 tx d0 serial port 0 output 12 14 8 p3.2 int0 external interrupt 0 13 15 9 p3.3 int1 external interrupt 1 14 16 10 p3.4 t0 timer 0 external input 15 17 11 p3.5 t1 timer 1 external input 16 18 12 p3.6 wr external data memory write strobe 17 19 13 p3.7 rd external data memory read strobe 31 35 29 ea ea - input. this pin must be connected to ground for proper operation. - 12 34 6 28 nc nc - reserved. these pins should not be connected. they are reserved for use with future devices in this family. - 1 39 nc - reserved. these pins are reserved for additional ground pins on future products. 80c32 compatibility the ds80c320/ds80c32 3 is a cmos 80c32 - compatible microcontroller designed for high performance. in most cases it will drop into an existing 80c32 design to significantly improve the operation. every effort has been made to keep the device familiar to 8032 users, yet it has ma ny new features. in general, software written for existing 80c32 - based systems will work on the ds80c320/ds80c323. the exception is critical timing since the high - speed microcontroller performs its instructions much faster than the original. it may be nece ssary to use memories with faster access times if the same crystal frequency is used. application note 57 ?ds80c320 memory interface timing? is a useful tool to help the embedded system designer select the proper memories for her or his application. the ds80c320/ds80c323 runs the standard 8051 instruction set and is pin - compatible with an 80c32 in any of three standard packages. it also provides the same timer/counter resources, full - duplex serial port, 256 bytes of scratchpad ram and i/o ports as the sta ndard 80c32. timers will default to a 12 clock per ds80c320/ds80c323 6 of 42 cycle operation to keep timing compatible with original 8051 systems. however, they can be programmed to run at the new 4 clocks per cycle if desired. new hardware features are accessed using special func tion registers that do not overlap with standard 80c32 locations. a summary of these sfrs is provided below. the ds80c320/ds80c323 addresses memory in an identical fashion to the standard 80c32. electrical timing will appear different due to the high - spee d nature of the product. however, the signals are essentially the same. detailed timing diagrams are provided below in the electrical specifications. this data sheet assumes the user is familiar with the basic features of the standard 80c32. in addition t o these standard features, the ds80c320/ds80c323 includes many new functions. this data sheet provides only a summary and overview. detailed descriptions are available in the user?s guide located in the front of the high - speed microcontroller data book. c omparative timing of the ds80c320/ds80c323 and 80c32 figure 2 ds80c320/ds80c323 timing standard 80c32 timing ds80c320/ds80c323 7 of 42 high - speed operation the ds80c320/ds80c323 is built around a high speed 80c32 compatible core. higher speed comes not just from increasing the clock frequency, but from a newer, more efficient design. in this updated core, dummy memory cycles have been eliminated. in a conventional 80c32, machine cycles are generated by dividing the clock frequency by 12. in the ds80c320/ds80c323, the same machi ne cycle is performed in 4 clocks. thus the fastest instruction, one machine cycle, is executed three times faster for the same crystal frequency. note that these are identical instructions. a comparison of the timing differences is shown in figure 2. the majority of instructions will see the full 3 to 1 speed improvement. some instructions will get between 1.5 and 2.4 x improvement. note that all instructions are faster than the original 80c51. table 2 below shows a summary of the instruction set includin g the speed. the numerical average of all opcodes is approximately a 2.5 to 1 speed improvement. individual programs will be affected differently, depending on the actual instructions used. speed - sensitive applications would make the most use of instructi ons that are three times faster. however, the sheer number of 3 to 1 improved opcodes makes dramatic speed improvements likely for any code. the dual data pointer feature also allows the user to eliminate wasted instructions when moving blocks of memory. instruction set summary all instructions in the ds80c320/ds80c323 perform the same functions as their 80c32 counterparts. their effect on bits, flags, and other status functions is identical. however, the timing of each instruction is different. this ap plies both in absolute and relative number of clocks. for absolute timing of real - time events, the timing of software loops will need to be calculated using the table below. however, counter/timers default to run at the older 12 clocks per increment. ther efore, while software runs at higher speed, timer - based events need no modification to operate as before. timers can be set to run at 4 clocks per increment cycle to take advantage of higher speed operation. the relative time of two instructions might be different in the new architecture than it was previously. for example, in the original architecture, the ?movx a, @dptr? instruction and the ?mov direct, direct? instruction used two machine cycles or 24 oscillator cycles. therefore, they required the same amount of time. in the ds80c320/ds80c323, the movx instruction can be done in two machine cycles or eight oscillator cycles but the ?mov direct, direct? uses three machine cycles or 12 oscillator cycles. while both are faster than their original counterpa rts, they now have different execution times from each other. this is because in most cases, the ds80c320/ds80c323 uses one cycle for each byte. the user concerned with precise program timing should examine the timing of each instruction for familiarity w ith the changes. note that a machine cycle now requires just four clocks, and provides one ale pulse per cycle. many instructions require only one cycle, but some require five. in the original architecture, all were one or two cycles except for mul and di v. ds80c320/ds80c323 8 of 42 instruction set summary table 2 legends: a - accumulator rn - register r7 - r0 direct - internal register address @ri - internal register pointed - to by r0 or r1 (except movx) rel - 2?s complement offset byte bit - direct bit - address #data - 8 - bit constan t #data 16 - 16 - bit constant addr 16 - 16 - bit destination address addr 11 - 11 - bit destination address oscillator oscillator instruction byte cycles instruction byte cycles arithmatic instructions: add a, rn 1 4 inc a 1 4 add a, direct 2 8 inc rn 1 4 add a, @ri 1 4 inc direct 2 8 add a, #data 2 8 inc @ri 1 4 addc a, rn 1 4 inc dptr 1 12 addc a, direct 2 8 dec a 1 4 addc a, @ri 1 4 dec rn 1 4 addc a, #data 2 8 dec direct 2 8 subb a, rn 1 4 dec @ri 1 4 subb a, direct 2 8 mul ab 1 20 subb a, @ri 1 4 div ab 1 20 subb a, #data 2 8 da a 1 4 logical instructions: anl a, rn 1 4 xrl a, rn 1 4 anl a, direct 2 8 xrl a, direct 2 8 anl a, @ri 1 4 xrl a, @ri 1 4 anl a, #data 2 8 xrl a, #data 2 8 anl direct, a 2 8 xrl direct , a 2 8 anl direct, #data 3 12 xrl direct, #data 3 12 orl a, rn 1 4 clr a 1 4 orl a, direct 2 8 cpl a 1 4 orl a, @ri 1 4 rl a 1 4 orl a, #data 2 8 rlc a 1 4 orl direct, a 2 8 rr a 1 4 orl direct, #data 3 12 rrc a 1 4 ds80c320/ds80c323 9 of 42 data transfer instructio ns: mov a, rn 1 4 movc a, @a+dptr 1 12 mov a, direct 2 8 movc a, @a+pc 1 12 mov a, @ri 1 4 movx a, @ri 1 8 - 36* mov a, #data 2 8 movx a, @dptr 1 8 - 36* mov rn, a 1 4 movx @ri, a 1 8 - 36* mov rn, direct 2 8 movx @dptr, a 1 8 - 36* mov rn, #data 2 8 p ush direct 2 8 mov direct, a 2 8 pop direct 2 8 mov direct, rn 2 8 xch a, rn 1 4 mov direct1, direct2 3 12 xch a, direct 2 8 mov direct, @ri 2 8 xch a, @ri 1 4 mov direct, #data 3 12 xchd a, @ri 1 4 mov @ri, a 1 4 mov @ri, direct 2 8 mov @ri, #data 2 8 mov dptr, #data 16 3 12 *user selectable bit manipulation instructions: clr c 1 4 anl c, bit 2 8 clr bit 2 8 anl c, bit 2 8 setb c 1 4 orl c, bit 2 8 setb bit 2 8 orl c , bit 2 8 cpl c 1 4 mov c, bit 2 8 cpl bit 2 8 mov bit, c 2 8 program branching instructions: acall addr 11 2 12 cjne a, direct, rel 3 16 lcall addr 16 3 16 cjne a, #data, rel 3 16 ret 1 16 cjne rn, #data, rel 3 16 reti 1 16 cjne ri, #data, rel 3 16 ajmp addr 11 2 12 nop 1 4 ljmp addr 16 3 16 jc rel 2 12 sjmp rel 2 12 jnc rel 2 12 jmp @a+dptr 1 12 jb bit, rel 3 16 jz rel 2 12 jnb bit, rel 3 16 jnz rel 2 12 jbc bit, rel 3 16 djnz rn, rel 2 12 djnz direc t, rel 3 16 the table above shows the speed for each class of instruction. note that many of the instructions have multiple opcodes. there are 255 opcodes for 111 instructions. of the 255 opcodes, 159 are three times faster than the original 80c32. w hile a system that emphasizes those instructions will see the most improvement, the large total number that receive a 3 to 1 improvement assure a dramatic speed increase for any system. the speed improvement summary is provided below. ds80c320/ds80c323 10 of 42 speed advantage summ ary #opcodes speed improvement 159 3.0 x 51 1.5 x 43 2.0 x 2 2.4 x 255 average: 2.5 memory access the ds80c320/ds80c323 contains no on - chip rom and 256 bytes of scratchpad ram. off - chip memory is accessed using the multiplexed address/data bus on p0 and t he msb address on p2. a typical memory connection is shown in figure 3. timing diagrams are provided in the electrical specifications. program memory (rom) is accessed at a fixed rate determined by the crystal frequency and the actual instructions. as ment ioned above, an instruction cycle requires 4 clocks. data memory (ram) is accessed according to a variable speed movx instruction as described below. typical memory connection figure 3 stretch memory cycle the ds80c320/ds80c323 allows the application software to adjust the speed of data memory access. the microcontroller is capable of performing the movx in as little as two instruction cycles. however, this value can be stretched as needed so that both fast memory and slow memory or peripherals can be accessed with no glue logic. even in high - speed systems, it may not be necessary or desirable to perform data memory access at full speed. in addition, there are a variety of memory mapped peripherals such as lcd displays or uarts that are not fast. the stretch movx is controlled by the clock control register at sfr location 8eh as described below. this allows the user to select a stretch value between 0 and 7. a stretch of 0 will result in a two - machine cycle movx. a stretch of 7 will result in a movx of nine machine cycles. software can dynamically change this value depending on the particular memory or peripheral. ds80c320/ds80c323 11 of 42 on reset, the stretch value will default to a 1, resulting in a three - cycle movx. therefore, ram access will not be performed at full speed. this is a convenience to existing designs that may not have fast ram in place. when maximum speed is desired, the software should select a stretch value of 0. when using very slow ram or peripherals, a larger stretch value can be selected. note that this affects data memory only and the only way to slow program memory (rom) access is to use a slower crystal. using a stretch value between 1 and 7 causes the microcontroller to stretch the read/write strobe and all related timing. this results in a wider re ad/write strobe allowing more time for memory/peripherals to respond. the timing of the variable speed movx is shown in the electrical specifications. note that full speed access is not the reset default case. table 3 below shows the resulting strobe width s for each stretch value. the memory stretch is implemented using the clock control special function register at sfr location 8eh. the stretch value is selected using bits ckcon.2 - 0. in the table, these bits are referred to as m2 through m0. the first stre tch (default) allows the use of common 120 ns or 150 ns rams without dramatically lengthening the memory access. data memory cycle stretch values table 3 ckcon.2 - 0 memory rd or wr strobe strobe width md2 md1 md0 cycles width in clocks time @ 25 mhz 0 0 0 2 2 80 ns 0 0 1 3 (default) 4 160 ns 0 1 0 4 8 320 ns 0 1 1 5 12 480 ns 1 0 0 6 16 640 ns 1 0 1 7 20 800 ns 1 1 0 8 24 960 ns 1 1 1 9 28 1120 ns ds80c320/ds80c323 12 of 42 dual data pointer data memory block moves can be accelera ted using the dual data pointer (dptr). the standard 8032 dptr is a 16 - bit value that is used to address off - chip data ram or peripherals. in the ds80c320/ds80c323, the standard 16 - bit data pointer is called dptr0 and is located at sfr addresses 82h and 83 h. these are the standard locations. the new dptr is located at sfr 84h and 85h and is called dptr1. the dptr select bit (dps) chooses the active pointer and is located at the lsb of the sfr location 86h. no other bits in register 86h have any effect and a re set to 0. the user switches between data pointers by toggling the lsb of register 86h. the increment (inc) instruction is the fastest way to accomplish this. all dptr - related instructions use the currently selected dptr for any activity. therefore only one instruction is required to switch from a source to a destination address. using the dual - data pointer saves code from needing to save source and destination addresses when doing a block move. once loaded, the software simply switches between dptr and 1 . the relevant register locations are as follows. dpl 82h low byte original dptr dph 83h high byte original dptr dpl1 84h low byte new dptr dph1 85h high byte new dptr dps 86h dptr select (lsb) sample code listed below illustrates the saving from using t he dual dptr. the example program was original code written for an 8051 and requires a total of 1869 ds80c320/ds80c323 machine cycles. this takes 299 s to execute at 25 mhz. the new code using the dual dptr requires only 1097 machine cycles taking 175.5 s. the dual dptr saves 772 machine cycles or 123.5 s for a 64 - byte block move. since each pass through the loop saves 12 machine cycles when compared to the single dptr approach, larger blocks gain more efficiency using this feature. 64 - byte block move w ithout dual data pointer ; sh and sl are high and low byte source address. ; dh and dl are high and low byte of destination address. # cycles mov r5, #64d ; number of bytes to move 2 mov dptr, #shsl ; load source address 3 mov r1, #sl ; save low byte of so urce 2 mov r2, #sh ; save high byte of source 2 mov r3, #dl ; save low byte of destination 2 mov r4, #dh ; save high byte of destination 2 move: ; this loop is performed the number of times loaded into r5, in this example 64 movx a, @dptr ; read source d ata byte 2 mov r1, dpl ; save new source pointer 2 mov r2, dph ; 2 mov dpl, r3 ; load new destination 2 mov dph, r4 ; 2 movx @dptr, a ; write data to destination 2 inc dptr ; next destination address 3 mov r3, dpl ; save new destination pointer 2 mov r4, d ph ; 2 mov dpl, r1 ; get new source pointer 2 mov dph, r2 ; 2 inc dptr ; next source address 3 djnz r5, move ; finished with table? 3 ds80c320/ds80c323 13 of 42 64 - byte block move with dual data pointer ; sh and sl are high and low byte source address. ; dh and dl are high and low b yte of destination address. ; dps is the data pointer select. reset condition is dps=0, dptr0 is selected. # cycles equ dps, #86h ; tell assembler about dps mov r5, #64 ; number of bytes to move 2 mov dptr, #dhdl ; load destination address 3 inc dps ; cha nge active dptr 2 mov dptr, #shsl ; load source address 2 move: ; this loop is performed the number of times loaded into r5, in this example 64 movx a, @dptr ; read source data byte 2 inc dps ; change dptr to destination 2 movx @dptr, a ; write data to d estination 2 inc dptr ; next destination address 3 inc dps ; change data pointer to source 2 inc dptr ; next source address 3 djnz r5, move ; finished with table? 3 peripheral overview peripherals in the ds80c320/ds80c323 are accessed using special functi on registers (sfrs). the device provides several of the most commonly needed peripheral functions in microcomputer - based systems. these functions are new to the 80c32 family and include a second serial port, power - fail reset, power - fail interrupt, and a pr ogrammable watchdog timer. these are described below, and more details are available in the high - speed microcontroller user?s guide. serial ports the ds80c320/ds80c323 provides a serial port (uart) that is identical to the 80c32. many applications require serial communication with multiple devices. therefore a second hardware serial port is provided that is a full duplicate of the standard one. it optionally uses pins p1.2 (rxd1) and p1.3 (txd1). this port has duplicate control functions included in new s fr locations. the second serial port operates in a comparable manner with the first. both can operate simultaneously but can be at different baud rates. the second serial port has similar control registers (scon1 at c0h, sbuf1 at c1h) to the original. on e difference is that for timer - based baud rates, the original serial port can use timer 1 or timer 2 to generate baud rates. this is selected via sfr bits. the new serial port can only use timer 1. timer rate control one important difference exists betwee n the ds80c320/ds80c323 and 80c32 regarding timers. the original 80c32 used a 12 clock per cycle scheme for timers and consequently for some serial baud rates (depending on the mode). the ds80c320/ds80c323 architecture normally runs using 4 clocks per cyc le. however, in the area of timers, it will default to a 12 - clock per cycle scheme on a reset. this allows existing code with real - time dependencies such as baud rates to operate properly. if an application needs higher speed timers or serial baud rates, t he timers can be set to run at the 4 - clock rate. the clock control register (ckcon - 8eh) determines these timer speeds. when the relevant ckcon bit is a logic 1, the device uses 4 clocks per cycle to generate timer speeds. when the control bit is set to a 0, the device uses 12 clocks for timer speeds. the reset condition is a 0. ckcon.5 selects the speed of ds80c320/ds80c323 14 of 42 timer 2. ckcon.4 selects timer 1 and ckcon.3 selects timer 0. note that unless a user desires very fast timing, it is unnecessary to alter these bits . note that the timer controls are independent. power - fail reset the ds80c320/ds80c323 incorporates a precision band - gap voltage reference to determine when v cc is out of tolerance. while powering up, internal circuits will hold the device in a reset stat e until v cc rises above the v rst reset threshold. once v cc is above this level, the oscillator will begin running. an internal reset circuit will then count 65536 clocks to allow time for power and the oscillator to stabilize. the microcontroller will then exit the reset condition. no external components are needed to generate a power on reset. during power - down or during a severe power glitch, as v cc falls below v rst , the microcontroller will also generate its own reset. it will hold the reset condition as long as power remains below the threshold. this reset will occur automatically, needing no action from the user or from the software. refer to the electrical specifications for the exact value of v rst . power - fail interrupt the same reference that generat es a precision reset threshold can also generate an optional early warning power - fail interrupt (pfi). when enabled by the application software, this interrupt always has the highest priority. on detecting that the v cc has dropped below v pfw and that the p fi is enabled, the processor will vector to rom address 0033h. the pfi enable is located in the watchdog control sfr (wdcon - d8h). setting wdcon.5 to a logic 1 will enable the pfi. the application software can also read a flag at wdcon.4. this bit is se t when a pfi condition has occurred. the flag is independent of the interrupt enable and software must manually clear it. watchdog timer for applications that can not afford to run out of control, the ds80c320/ds80c323 incorporates a programmable watchdog timer circuit. it resets the microcontroller if software fails to reset the watchdog before the selected time interval has elapsed. the user selects one of four timeout values. after enabling the watchdog, software must reset the timer prior to expiration of the interval, or the cpu will be reset. both the watchdog enable and the watchdog reset bits are protected by a ?timed access? circuit. this prevents accidentally clearing the watchdog. timeout values are precise since they are related to the crystal f requency as shown below in table 4. for reference, the time periods at 25 mhz are also shown. the watchdog timer also provides a useful option for systems that may not require a reset. if enabled, then 512 clocks before giving a reset, the watchdog will g ive an interrupt. the interrupt can also serve as a convenient time - base generator, or be used to wake - up the processor from idle mode. the watchdog function is controlled in the clock control (ckcon - 8eh), watchdog control (wdcon - d8h), and extended int errupt enable (eie - e8h) sfrs. ckcon.7 and ckcon.6 are called wd1 and wd0 respectively and are used to select the watchdog timeout period as shown in table 4. watchdog timeout values table 4 interrupt time reset time wd1 wd0 timeout (@25 mhz) timeout (@25 mhz) 0 0 2 17 clocks 5.243 ms 2 17 + 512 clocks 5.263 ms j 0 1 2 20 clocks 41.94 ms 2 20 + 512 clocks 41.96 ms 1 0 2 23 clocks 335.54 ms 2 23 + 512 clocks 335.56 ms 1 1 2 26 clocks 2684.35 ms 2 26 + 512 clocks 2684.38 ms ds80c320/ds80c323 15 of 42 as shown above, the watchdog tim er uses the crystal frequency as a time base. a user selects one of four counter values to determine the timeout. these clock counter lengths are 2 17 = 131,072 clocks; 2 20 = 1,048,576; 2 23 = 8,388,608 clocks; or 2 26 = 67,108,864 clocks. the times shown in tab le 4 are with a 25 mhz crystal frequency. note that once the counter chain has reached a conclusion, the optional interrupt is generated. regardless of whether the user enables this interrupt, there are then 512 clocks left until a reset occurs. there are 5 control bits in special function registers that affect the watchdog timer and two status flags that report to the user. the reset watchdog timer bit (wdcon.0) should be asserted prior to modifying the watchdog timer mode select bits (wd1, wd0) to avoid c orruption of the watchdog count. wdif (wdcon.3) is the interrupt flag that is set when there are 512 clocks remaining until a reset occurs. wtrf (wdcon.2) is the flag that is set when a watchdog reset has occurred. this allows the application software to determine the source of a reset. setting the ewt (wdcon.1) bit enables the watchdog timer. the bit is protected by timed access discussed below. setting the rwt (wdcon.0) bit restarts the watchdog timer for another full interval. application software mus t set this bit prior to the timeout. as mentioned previously, wd1 and 0 (ckcon .7 and 6) select the timeout. finally, the watchdog interrupt is enabled using ewdi (eie.4). interrupts the ds80c320/ds80c323 provides 13 sources of interrupt with three priori ty levels. the power - fail interrupt (pfi), if enabled, always has the highest priority. there are two remaining user selectable priorities: high and low. if two interrupts that have the same priority occur simultaneously, the natural precedence given belo w determines which is a acted upon. except for the pfi, all interrupts that are new to the 8051 family have a lower natural priority than the originals. interrupt priority table 5 name description vector natural priority old/new pfi power - fail intterupt 33h j 1 new int0 external interrupt 0 03h 2 old tf0 timer 0 0bh 3 old int1 external interrupt 1 13h 4 old tf1 timer 1 1bh 5 old scon0 ti0 or ri0 from serial port 0 23h 6 old tf2 timer 2 2bh 7 old scon1 ti1 or ri 1 from serial port 1 3bh 8 new int2 external interrupt 2 43h 9 new int3 external interrupt 3 4bh 10 new int4 external interrupt 4 53h 11 new int5 external interrupt 5 5bh 12 new wdti watchdog timeout interrupt 63h 13 new ds80c320/ds80c323 16 of 42 power management the ds80c320/ds80c323 provides the standard idle and power - down (stop) that are available on the standard 80c32. however the device has enhancements that make these modes more useful, and allow more power saving. the idle mode i s invoked by setting the lsb of the power control register (pcon - 87h). idle will leave internal clocks, serial port and timer running. no memory access will be performed so power is dramatically reduced. since clocks are running, the idle power consumpti on is related to crystal frequency. it should be approximately ? of the operational power. the cpu can exit the idle state with any interrupt or a reset. the power - down or stop mode is invoked by setting the pcon.1 bit. stop mode is a lower power state th an idle since it turns off all internal clocking. the i cc of a standard stop mode is approximately 1 a but is specified in the electrical specifications. the cpu will exit stop mode from an external interrupt or a reset condition. note that internally ge nerated interrupts (timer, serial port, watchdog) are not useful in idle or stop since they require clocking activity. idle mode enhancements a simple enhancement to idle mode makes it substantially more useful. the innovation involves not the idle mode i tself, but the watchdog timer. as mentioned above, the watchdog timer provides an optional interrupt capability. this interrupt can provide a periodic interval timer to bring the ds80c320/ds80c323 out of idle mode. this can be useful even if the watchdog i s not normally used. by enabling the watchdog timer and its interrupt prior to invoking idle, a user can periodically come out of idle perform an operation, then return to idle until the next operation. this will lower the overall power consumption. when u sing the watchdog interrupt to cancel the idle state, make sure to restart the watchdog timer or it will cause a reset. stop mode enhancements the ds80c320/ds80c323 provides two enhancements to the stop mode. as documented above, the device provides a ban d - gap reference to determine power - fail interrupt and reset thresholds. the default state is that the band - gap reference is off when stop mode is invoked. this allows the extremely low power state mentioned above. a user can optionally choose to have the b and - gap enabled during stop mode. this means that pfi and power - fail reset will be activated and are valid means for leaving stop mode. in stop mode with the band - gap on, i cc will be approximately 50 a compared with 1 a with the band - gap off. if a user does not require a power - fail reset or interrupt while in stop mode, the band - gap can remain turned off. note that only the most power sensitive applications should turn off the band - gap, as this results in an uncontrolled power down condition. the contr ol of the band - gap reference is located in the extended interrupt flag register (exif - 91h). setting bgs (exif.0) to a 1 will leave the band - gap reference enabled during stop mode. the default or reset condition is with the bit at a logic 0. this results in the band - gap being turned off during stop mode. note that this bit has no control of the reference during full power or idle modes. ds80c320/ds80c323 17 of 42 the second feature allows an additional power saving option. this is the ability to start instantly when exiting stop mo de. it is accomplished using an internal ring oscillator that can be used when exiting stop mode in response to an interrupt. the benefit of the ring oscillator is as follows. using stop mode turns off the crystal oscillator and all internal clocks to save power. this requires that the oscillator be restarted when exiting stop mode. actual start - up time is crystal dependent, but is normally at least 4 ms. a common recommendation is 10 ms. in an application that will wake - up, perform a short operation, then return to sleep, the crystal start - up can be longer than the real transaction. however, the ring oscillator will start instantly. the user can perform a simple operation and return to sleep before the crystal has even stabilized. if the ring is used to st art and the processor remains running, hardware will automatically switch to the crystal once a power - on reset interval (65536 clocks) has expired. this value is used to guarantee stability even though power is not being cycled. if the user returns to sto p mode prior to switching of crystal, then all clocks will be turned off again. the ring oscillator runs at approximately 3 mhz (1.5 mhz at 3v) but will not be a precision value. no real - time precision operations (including serial communication) should be conducted during this ring period. figure 7 shows how the operation would compare when using the ring, and when starting up normally. the default state is to come out of stop mode without using the ring oscillator. this function is controlled using the rg sl - ring select bit at exif.1 (exif - 91h). when exif.1 is set, the ring oscillator will be used to come out of stop mode quickly. as mentioned above, the processor will automatically switch from the ring (if enabled) to the crystal after a delay of 65536 crystal clocks. for a 3.57 mhz crystal, this is approximately 18 ms. the processor sets a flag called rgmd - ring mode to tell software that the ring is being used. this bit at exif.2 will be a logic 1 when the ring is in use. no serial communication or p recision timing should be attempted while this bit is set, since the operating frequency is not precise. ring oscillator start - up figure 4 diagram assumes that the operation following stop requires less than 18 ms complete. ds80c320/ds80c323 18 of 42 timed access protection sel ected sfr bits are critical to operation, making it desirable to protect against an accidental write operation. the timed access procedure prevents an errant cpu from accidentally altering a bit that would cause difficulty. the timed access procedure req uires that the write of a protected bit be preceded by the following instructions: mov 0c7h, #0aah mov 0c7h, #55h by writing an aah followed by a 55h to the timed access register (location c7h), the hardware opens a three - cycle window that allows softwar e to modify one of the protected bits. if the instruction that seeks to modify the protected bit is not immediately proceeded by these instructions, the write will not take effect. the protected bits are: exif.0 bgs band - gap select wdcon.6 por power - on re set flag wdcon.1 ewt enable watchdog wdcon.0 rwt reset watchdog wdcon.3 wdif watchdog interrupt flag special function registers most special features of the ds80c320/ds80c323 or 80c32 are controlled by bits in special function registers (sfrs). this allow s the device to add many features but use the same instruction set. when writing software to use a new feature, the sfr must be defined to an assembler or compiler using an equate statement. this is the only change needed to access the new function. the d s80c320/ds80c323 duplicates the sfrs that are contained in the standard 80c32. table 6 shows the register addresses and bit locations. many are standard 80c32 registers. the high - speed microcontroller user?s guide describes all sfrs. ds80c320/ds80c323 19 of 42 special function regi ster locations table 6 register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 address sp 81h dpl 82h dph 83h dpl1 84h dph1 85h dps 0 0 0 0 0 0 0 sel 86h pcon smod_0 smod0 - - gf1 gf0 stop idle 87h tcon tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 88h tmod gate c/ t m1 m0 gate c/ t m1 m0 89h tl0 8ah tl1 8bh th0 8ch th1 8dh ckcon wd1 wd0 t2m t1m t0m md2 md1 md0 8eh p1 p1.7 p1.6 p1.5 p1.4 p1.3 p1.2 p1.1 p1.0 90h exif ie5 ie4 ie3 ie2 - rgmd rgsl bgs 91h scon0 sm0/fe_0 sm1_0 sm2_0 ren_0 tb8_0 rb8_0 ti_0 ri_0 98h sbuf0 99h p2 p2.0 p2.6 p2.5 p2.4 p2.3 p2.2 p2.1 p2.0 a0h ie ea es1 et2 es0 et1 ex1 et0 ex0 a8h saddr0 a9h saddr1 aah p3 p3.7 p3.6 p3.5 p3.4 p3.3 p3.2 p3.1 p3.0 b0h ip - ps1 pt2 ps0 pt1 px1 pt0 px0 b8h saden0 b9h saden1 bah scon1 sm0/fe_0 sm1_0 sm2_0 ren_0 tb8_0 rb8_0 ti_0 ri_0 c0h sbuf1 c1h status pip hip lip 1 1 1 1 1 c5h ta c7h t2con tf2 exf2 rclk tclk exen2 tr2 c/ t2 cp/ rl2 c8h t2mod - - - - - - t2oe dcen c9h rcap2l cah rcap2h cbh tl2 cch th2 cdh psw cy ac f0 rs1 rs0 ov fl p d0h wdcon smod_ 1 por epfi pfi wdif wtrf ewt rwt d8h acc e0h eie - - - ewdi ex5 ex4 ex3 ex2 e8h b f0h eip - - - pwdi px5 px4 px3 px2 f8h ds80c320/ds80c323 20 of 42 electrical specifications absolute maximum ratings* voltage on any pin relative to ground - 0.3v to (vcc + 0.5v) voltage on vcc relative to ground - 0.3v to +6.0v operating temperature - 40 c to +85 c storage temperature - 55 c to +125 c soldering temperature 160 c for 10 seconds * this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. ds80c320 dc electrical characteristics parameter symbol mi n typ max units notes operating supply voltage v cc 4.5 5.0 5.5 v 1 power - fail warning v pfw 4.25 4.38 4.55 v 1 minimum operating voltage v rst 4.0 4.1 4.25 v 1, 12 supply current active mode @ 25 mhz i cc 30 45 ma 2 supply current idle mode @ 25 mhz i id le 15 25 ma 3 supply current active mode @ 33 mhz i cc 35 ma 2 supply current idle mode @ 33 mhz i idle 20 ma 3 supply current stop mode, band - gap reference disabled i stop .01 1 a 4 supply current stop mode, band - gap reference enabled i spbg 50 80 a 4, 10 input low level v il - 0.3 +0.8 v 1 input high level (except xtal1 and rst) v ih1 2.0 v cc +0.3 v 1 input high level xtal1 and rst v ih2 3.5 v cc +0.3 v 1 output low voltage ports 1, 3, @ i ol = 1.6 ma v ol1 0.45 v 1 output low voltage ports 0, 2 , ale, psen @ i ol = 3.2 ma v ol2 0.45 v 1, 5 output high voltage ports 1, 3, ale, psen @ i oh = - 50 a v oh1 2.4 v 1, 6 output high voltage ports 1, 3, @ i oh = - 1.5 ma v oh2 2.4 v 1, 7 output high voltage ports 0, 2, ale, psen @ i oh = - 8 ma v oh3 2.4 v 1, 5 input low current ports 1, 3 @ 0.45v i il - 55 a 11 transition current from 1 to 0 ports 1, 3 @ 2v i tl - 650 a 8 input leakage port 0, bus mode i l - 300 +300 a 9 rst pulldown resistan ce r rst 50 170 ko ds80c320/ds80c323 21 of 42 notes for ds80c320 dc electrical characteristics: all parameters apply to both commercial and industrial temperature operation unless otherwise noted. 1. all voltages are referenced to ground. 2. active current is measured with a 25 mhz cl ock source driving xtal1, v cc =rst=5.5v, all other pins disconnected. 3. idle mode current is measured with a 25 mhz clock source driving xtal1, v cc =5.5v, rst at ground, all other pins disconnected. 4. stop mode current measured with xtal1 and rst grounded, v cc =5.5v, all other pins disconnected. when addressing external memory. 5. when addressing external memory. 6. rst=v cc . this condition mimics operation of pins in i/o mode. 7. during a 0 to 1 transition, a one - shot drives the ports hard for two clock cycles. this m easurement reflects port in transition mode. 8. ports 1, 2, and 3 source transition current when being pulled down externally. it reaches its maximum at approximately 2v. 9. 0.45 ds80c320/ds80c323 23 of 42 notes for ac electr ical characteristics: all parameters apply to both commercial and industrial temperature range operation unless otherwise noted. ac timing characteristics valid for oscillator frequency > 16 mhz. 1. all signals rated over operating temperature at 25 mhz. 2. al l signals characterized with load capacitance of 80 pf except port 0, ale, psen , rd and wr at 100 pf. note that loading should be approximately equal for valid timing. 3. interfacing to memory dev ices with float times (turn off times) over 35 ns may cause contention. this will not damage the parts, but will cause an increase in operating current. 4. specifications assume a 50% duty cycle for the oscillator. port 2 timing will change with the duty cyc le variations. 5. address is held in a weak latch until over - driven by external memory. ds80c320/ds80c323 24 of 42 ds80c320 movx characteristics up to 25 mhz parameter symbol variable clock min variable clock max units stretch rd pulse width t rlrh 2t clcl - 11 t mcs - 11 ns t mcs =0 t mcs >0 wr pulse width t wlwh 2t clcl - 11 t mcs - 11 ns t mcs =0 t mcs >0 rd low to valid data in t rldv 2t clcl - 25 t mcs - 25 ns t mcs =0 t mcs >0 data hold after read t rhdx 0 ns data float after read t rhdz t c lcl - 5 2t clcl - 5 ns t mcs =0 t mcs >0 ale low to valid data in t lldv 2.5t clcl - 26 1.5t clcl - 28+t mcs ns t mcs =0 t mcs >0 port 0 address to valid data in t avdv1 3t clcl - 24 2t clcl - 31+t mcs ns t mcs =0 t mcs >0 port 2 address to valid data in t avdv2 3.5t clcl - 32 2.5t clcl - 34+t mcs ns t mcs =0 t mcs >0 ale low to rd or wr low t llwl 0.5t clcl - 5 1.5t clcl - 5 0.5t clcl +6 1.5t clcl +8 ns t mcs =0 t mcs >0 port 0 address valid to rd or wr low t avwl1 t clcl - 9 2t clcl - 10 ns t mcs =0 t mcs >0 port 2 address valid to rd or wr low t avwl2 1.5t clcl - 9 2.5t clcl - 13 ns t mcs =0 t mcs >0 data valid to wr transition t qvwx - 9 t clcl - 10 ns t mcs =0 t mcs >0 data hold after write t whqx t clcl - 7 2t clcl - 5 ns t mcs =0 t mcs >0 rd low to address float t rlaz note 5 ns rd or wr high to ale high t whlh 0 t clcl - 5 10 t clcl +11 ns t mcs =0 t mcs >0 note: t mcs is a time period r elated to the stretch memory cycle selection. the following table shows the value of t mcs for each stretch selection. m2 m1 m0 movx cycles t mcs 0 0 0 2 machine cycles 0 0 0 1 3 machine cycles (default) 4 t clcl 0 1 0 4 machine cycles 8 t clcl 0 1 1 5 ma chine cycles 12 t clcl 1 0 0 6 machine cycles 16 t clcl 1 0 1 7 machine cycles 20 t clcl 1 1 0 8 machine cycles 24 t clcl 1 1 1 9 machine cycles 28 t clcl ds80c320/ds80c323 25 of 42 ds80c320 ac characteristics up to 33 mhz parameter symbol 33 mhz min 33 mhz max variable clock min v ariable clock max units oscillator frequency (ext. osc.) (ext. crystal) 1/t clcl 0 1 33 33 0 1 33 33 mhz ale pulse width t lhll 35 1.5t clcl - 10 ns port 0 address valid to ale low t avll 4 0.5t clcl - 11 ns address hold after ale low t llax1 2 note 5 0.25t clcl - 5 note 5 ns address hold after ale low for movx wr t llax2 8 0.5t clcl - 7 ns ale low to valid instruction in t lliv 49 2.5t clcl - 27 ns ale low to psen low t llpl 0.5 0.25t clcl - 7 ns psen pulse width t plph 61 2.25t clcl - 7 ns psen low to valid instruction in t pliv 48 2.25t clcl - 21 ns input instruction hold after psen t pxix 0 0 ns input instruction float after psen t pxiz 25 t clcl - 5 ns port 0 address to valid instruction in t aviv1 64 3t clcl - 27 ns port 2 address to valid instruction in t aviv2 73 3.5t clcl - 33 ns psen low to address float t plaz note 5 note 5 ns notes for ds80c323 ac electrical charac teristics: all parameters apply to both commercial and industrial temperature range operation unless otherwise noted. ac timing characteristics valid for oscillator frequency > 16 mhz. 1. all signals rated over operating temperature at 33 mhz. 2. all signals c haracterized with load capacitance of 80 pf except port 0, ale, psen , rd and wr at 100 pf. note that loading should be approximately equal for valid timing. 3. interfacing to memory devices with f loat times (turn off times) over 30 ns may cause contention. this will not damage the parts but will cause an increase in operating current. 4. specifications assume a 50% duty cycle for the oscillator. port 2 timing will change with the duty cycle variation s. 5. address is held in a weak latch until over driven by external memory. ds80c320/ds80c323 26 of 42 ds80c320 movx characteristics up to 33 mhz parameter symbol variable clock min variable clock max units stretch rd pulse width t rlrh 2t clcl - 11 t mcs - 11 ns t mcs =0 t mcs >0 wr pulse width t wlwh 2t clcl - 11 t mcs - 11 ns t mcs =0 t mcs >0 rd low to valid data in t rldv 2t clcl - 25 t mcs - 25 ns t mcs =0 t mcs >0 data hold after read t rhdx 0 ns data float after read t rhdz t clcl - 5 2t clcl - 5 ns t mcs =0 t mcs >0 ale low to valid data in t lldv 2.5t clcl - 26 1.5t clcl - 28+t mcs ns t mcs =0 t mcs >0 port 0 address to valid data in t avdv1 3t clcl - 24 2t clcl - 31+t mcs ns t mcs =0 t mcs >0 port 2 address to valid data in t avdv2 3.5t clcl - 32 2.5t clcl - 34+t mcs ns t mcs =0 t mcs >0 ale low to rd or wr low t llwl 0.5t clcl - 5 1.5t clcl - 5 0.5t clcl +6 1.5t clcl +8 ns t mcs =0 t mcs >0 port 0 address valid to rd or wr low t avwl1 t clcl - 9 2t clcl - 10 ns t mcs =0 t mcs >0 port 2 address valid to rd or wr low t avwl2 1.5t clcl - 9 2.5t clcl - 13 ns t mcs =0 t mcs >0 data valid to wr transition t qvwx - 9 t clcl - 10 ns t mcs =0 t mcs >0 data hold after write t whqx t clcl - 7 2t clcl - 5 ns t mcs =0 t mcs >0 rd low to address float t rlaz note 5 ns rd or wr high to ale high t whlh 0 t clcl - 5 10 t clcl +11 ns t mcs =0 t mcs >0 note: t mcs is a time period related to th e stretch memory cycle selection. the following table shows the value of t mcs for each stretch selection. m2 m1 m0 movx cycles t mcs 0 0 0 2 machine cycles 0 0 0 1 3 machine cycles (default) 4 t clcl 0 1 0 4 machine cycles 8 t clcl 0 1 1 5 machine cycles 12 t clcl 1 0 0 6 machine cycles 16 t clcl 1 0 1 7 machine cycles 20 t clcl 1 1 0 8 machine cycles 24 t clcl 1 1 1 9 machine cycles 28 t clcl ds80c320/ds80c323 27 of 42 ds80c323 dc electrical characteristics parameter symbol min typ max units notes operating supply voltage v cc 2. 7 3.0 5.5 v 1 power - fail warning v pfw 2.6 2.7 2.8 v 1 minimum operating voltage v rst 2.5 2.6 2.7 v 1, 12 supply current active mode @ 18 mhz i cc 10 ma 2 supply current idle mode @ 18 mhz i idle 6 ma 3 supply current stop mode, band - gap reference di sabled i stop 0.1 a 2 supply current stop mode, band - gap reference enabled i spbg 40 a 4, 10 input low level v il - 0.3 0.2 v cc v 1 input high level (except xtal1 and rst) v ih1 0.7 v cc v cc +0.3 v 1 input high level xtal1 and rst v ih2 0.7 v cc +0.25v v cc +0.3 v 1 output low voltage ports 1, 3, @ i ol = 1.6 ma v ol1 0.4 v 1 output low voltage ports 0, 2, psen /ale @ i ol = 3.2 ma v ol2 0.4 v 1, 5 output high voltage ports 1, 3, psen /ale @ i oh = - 15 a v oh1 v dd - 0. 4v v 1, 6 output high voltage ports 1, 3, @ i oh = - 1.5 ma v oh2 v dd - 0.4v v 1, 7 output high voltage ports 0, 2, psen /ale @ i oh = - 2 ma v oh3 v dd - 0.4v v 1, 5 input low current ports 1, 3, @ 0.45v i il - 30 a 11 transition curre nt from 1 3 0, ports 1, 3 @ 2v i tl - 400 a 8 input leakage port 0, bus mode i l - 300 +300 a 9 rst pulldown resistance r rst 50 170 ko notes for ds80c323 dc electrical characteristics: all parameters apply to both commercial and industrial temperatu re operation unless otherwise noted. device operating range is 2.7v - 5.5v. dc electrical specifications are for operation 2.7v - 3.3v. 1. all voltages are referenced to ground. 2. active mode current is measured with an 18 mhz clock source driving xtal1, v cc = rst=3.3v, all other pins disconnected. 3. idle mode current is measured with an 18 mhz clock source driving xtal1, v cc =3.3v, all other pins disconnected. 4. stop mode current measured with xtal1 and rst grounded, v cc =3.3v, all other pins disconnected. ds80c320/ds80c323 28 of 42 5. when a ddressing external memory. 6. rst= v cc . this condition mimics operation of pins in i/o mode. 7. during a 0 to 1 transition, a one - shot drives the ports hard for two clock cycles. this measurement reflects port in transition mode. 8. ports 1, 2, and 3 source tran sition current when being pulled down externally. it reaches its maximum at approximately 2v. 9. v in between ground and v cc - 0.3v. not a high impedance input. this port is a weak address latch because port 0 is dedicated as an address bus on the ds80c323. p eak current occurs near the input transition point of the latch, approximately 2v. 10. over the industrial temperature range, this specification has a maximum value of 200 a. 11. this is the current from an external circuit to hold a logic low level on an i/o p in while the corresponding port latch bit is set to 1. this is only the current required to hold the low level; transitions from 1 to 0 on an i/o pin will also have to overcome the transition current. 12. device operating range is 2.7v to 5.5v, however device is tested to 2.5v to ensure proper operation at minimum v rst . ds80c320/ds80c323 29 of 42 ds80c323 ac electrical characteristics parameter symbol 18 mhz min 18 mhz max variable clock min variable clock max units oscillator frequency (ext. osc.) (ext. crystal) 1/t clcl 0 1 18 18 0 1 18 18 mhz ale pulse width t lhll 73 1.5t clcl - 10 ns port 0 address valid to ale low t avll 16 0.5t clcl - 11 ns address hold after ale low t llax1 8 note 5 0.25t clcl - 5 note 5 ns address hold after ale low for movx wr t llax2 20 0.5t clcl - 7 ns ale low to valid instruction in t lliv 112 2.5t clcl - 27 ns ale low to psen low t llpl 6 0.25t clcl - 7 ns psen pulse width t plph 118 2.25t clcl - 7 ns psen low to valid instruction i n t pliv 104 2.25t clcl - 21 ns input instruction hold after psen t pxix 0 0 ns input instruction float after psen t pxiz 51 t clcl - 5 ns port 0 address to valid instruction in t aviv1 140 3t clcl - 27 ns port 2 addres s to valid instruction in t aviv2 162 3.5t clcl - 33 ns psen low to address float t plaz note 5 note 5 ns notes for ds80c323 ac electrical characteristics: all parameters apply to both commercial and industrial temperature range operat ion unless otherwise noted. ac timing characteristics valid for oscillator frequency > 16 mhz. 1. all signals rated over operating temperature at 18 mhz. 2. all signals characterized with load capacitance of 80 pf except port 0, ale, psen , rd and wr at 100 pf. note that loading should be approximately equal for valid timing. 3. interfacing to memory devices with float times (turn off times) over 35 ns may cause contention. this will not damage the parts , but will cause an increase in operating current. 4. specifications assume a 50% duty cycle for the oscillator. port 2 timing will change with the duty cycle variations. 5. address is held in a weak latch until over - driven by external memory. ds80c320/ds80c323 30 of 42 ds80c323 movx c haracteristics parameter symbol variable clock min variable clock max units stretch rd pulse width t rlrh 2t clcl - 11 t mcs - 11 ns t mcs =0 t mcs >0 wr pulse width t wlwh 2t clcl - 11 t mcs - 11 ns t mcs =0 t mcs >0 rd low to valid data in t rldv 2t clcl - 25 t mcs - 25 ns t mcs =0 t mcs >0 data hold after read t rhdx 0 ns data float after read t rhdz t clcl - 5 2t clcl - 5 ns t mcs =0 t mcs >0 ale low to valid data in t lldv 2.5t clcl - 26 1.5t clcl - 28+t mcs ns t mcs =0 t mcs >0 por t 0 address to valid data in t avdv1 3t clcl - 24 2t clcl - 31+t mcs ns t mcs =0 t mcs >0 port 2 address to valid data in t avdv2 3.5t clcl - 32 2.5t clcl - 34+t mcs ns t mcs =0 t mcs >0 ale low to rd or wr low t llwl 0.5t clcl - 5 1.5t cl cl - 5 0.5t clcl +6 1.5t clcl +8 ns t mcs =0 t mcs >0 port 0 address valid to rd or wr low t avwl1 t clcl - 9 2t clcl - 10 ns t mcs =0 t mcs >0 port 2 address valid to rd or wr low t avwl2 1. 5t clcl - 9 2.5t clcl - 13 ns t mcs =0 t mcs >0 data valid to wr transition t qvwx - 9 t clcl - 10 ns t mcs =0 t mcs >0 data hold after write t whqx t clcl - 7 2t clcl - 5 ns t mcs =0 t mcs >0 rd low to address float t rlaz note 5 ns rd or wr high to ale high t whlh 0 t clcl - 5 10 t clcl +11 ns t mcs =0 t mcs >0 note: t mcs is a time period related to the stretch memory cycle selection. the following table shows the value of t mcs for each stretch selectio n. m2 m1 m0 movx cycles t mcs 0 0 0 2 machine cycles 0 0 0 1 3 machine cycles (default) 4 t clcl 0 1 0 4 machine cycles 8 t clcl 0 1 1 5 machine cycles 12 t clcl 1 0 0 6 machine cycles 16 t clcl 1 0 1 7 machine cycles 20 t clcl 1 1 0 8 machine cycles 24 t clcl 1 1 1 9 machine cycles 28 t clcl ds80c320/ds80c323 31 of 42 ds80c320/ds80c323 external clock characteristics parameter symbol min typ max units notes clock high time t chcx 10 ns clock low time t clcx 10 ns clock rise time t clch 5 ns clock fall time t chcl 5 ns ds80c320/ds80c323 serial port mode 0 timing characteristics parameter symbol min typ max units notes serial port clock cycle time sm2=0 12 clocks per cycle sm2=1 4 clocks per cycle t xlxl 12t clcl 4t clcl ns output data setup to clock rising edge sm2=0 12 clocks per cycle sm2=1 4 clocks per cycle t qvxh 10t clcl 3t clcl ns output data hold from clock rising sm2=0 12 clocks per cycle sm2=1 4 clocks per cycle t xhqx 2t clcl t clcl ns input data hold after clock rising sm2=0 12 clocks per cycle sm2=1 4 c locks per cycle t xhdx t clcl t clcl ns clock rising edge to input data valid sm2=0 12 clocks per cycle sm2=1 4 clocks per cycle t xhdv 11t clcl 2t clcl ns explanation of ac symbols in an effort to remain compatible with the original 8051 family, this d evice specifies the same parameter as such devices, using the same symbols. for completeness, the following is an explanation of the symbols. t time a address c clock d input data h logic level high l logic level low i instruction p psen q output data r rd signal v valid w wr signal x no longer a valid logic level z tristate ds80c320/ds80c323 32 of 42 ds80c320/ds80c323 power cycle timing characteristics parameter symbol min typ max units notes crystal start - up time t csu 1.8 ms 1 power - on reset delay t por 65536 t clcl 2 notes for power cycle timing characteristics: 1. start - up time for crystals varies with load capacitance and manufacturer. time shown is for an 11.0592 mhz crystal manufactured by fox crystal. 2. reset del ay is a synchronous counter of crystal oscillations after crystal start - up. counting begins when the level on the xtal1 input meets the v ih2 criteria. at 25 mhz, this time is 2.62 ms. program memory read cycle ds80c320/ds80c323 33 of 42 data memory read cycle data memory w rite cycle ds80c320/ds80c323 34 of 42 data memory write with stretch=1 ds80c320/ds80c323 35 of 42 data memory write with stretch=2 four cycle data memory write stretch value=2 external clock drive ds80c320/ds80c323 36 of 42 serial port mode 0 timing serial port 0 (synchronous mode) high speed operation sm2=1=> txd clo ck=xtal/4 serial port 0 (synchronous mode) sm2=0=> txd clock=xtal/12 ds80c320/ds80c323 37 of 42 power cycle timing ds80c320/ds80c323 38 of 42 40 - pin pdip (600 - mil) all dimensions are in inches. pkg 40 - pin dim min max a - 0.200 a1 0.015 - a2 0.140 0.160 b 0.014 0.022 c 0.008 0.012 d 1. 980 2.085 e 0.600 0.625 e1 0.530 0.555 e 0.090 0.110 l 0.115 0.145 eb 0.600 0.700 56 - g5000 - 000 ds80c320/ds80c323 39 of 42 44 - pin tqfp pkg 44 - pin dim min max a - 1.20 a1 0.05 0.15 a2 0.95 1.05 d 11.80 12.20 d1 10.00 bsc e 11.80 12.20 e1 10.00 bsc l 0.45 0.75 e 0.80 bsc b 0.30 0.45 c 0 .09 0.20 56 - g4012 - 001 notes: 1. dimensions d1 and e1 include mold mismatch, but do not include mold protrusion; allowable protrusion is 0.25 mm per side. 2. details of pin 1 identifier are optional but must be located within the zone indicated. 3. allowab le dambar protrusion is 0.08 mm total in excess of the b dimension; at maximum material condition. protrusion not to be located on lower radius or foot of lead. 4. controlling dimensions: millimeters. ds80c320/ds80c323 40 of 42 44 - pin plcc pkg 44 - pin dim min max a 0.165 0.180 a1 0.090 0.120 a2 0.020 - b 0.026 0.033 b1 0.013 0.021 c 0.009 0.012 ch1 0.042 0.048 d 0.685 0.695 d1 0.650 0.656 d2 0.590 0.630 e 0.685 0.695 e1 0.650 0.656 e2 0.590 0.630 e1 0.050 bsc n 0.44 - 56 - g4003 - 001 notes: 1. pin - 1 identifier to be located in zone indicated . 2. controlling dimensions are in inches. ds80c320/ds80c323 41 of 42 data sheet revision summary the following represent the key differences betw een the 041896 and the 052799 version of the ds80c320 data sheet. please review this summary carefully. 1. corrected v cc pin description to show ds80c323 operation at +3v. 2. corrected timed access description to show three cycle window. 3. modified absolute max imum ratings for any pin relative to around, v cc relative to ground. 4. changed minimum oscillator frequency to 1 mhz when using external crystal. 5. clarified that t por begins when xtal1 reaches v ih2 . the following represent the key differences between the 1 03196 and the 041896 version of the ds80c320 data sheet. please review this summary carefully. 1. update ds80c320 25 mhz ac characteristics. the following represent the key differences between the 041895 and the 031096 version of the ds80c320 data sheet. pl ease review this summary carefully. 1. remove port 0, port 2 from v oh1 specification (pcn b60802). 2. v oh1 test specification clarified (rst = v cc ). 3. add t avwl2 marking to external memory read cycle figure. 4. correct tqfp drawing to read 44 - pin tqfp. 5. rotate page 1 tqfp illustration to match assembly specifications. the following represent the key differences between the 031096 and the 052296 version of the ds80c320 data sheet. please review this summary carefully. 1. add data sheet revision summary. the following r epresent the key differences between 05/23/96 and 05/22/96 version of the ds80c320 data sheet and between 05/23/96 and 03/27/95 version of the ds80c323 data sheet. please review this summary carefully. ds80c320: 1. add ds80c323 characteristics. 2. change ds80c3 20 v pfw specification from 4.5v to 4.55v (pcn e62802). 3. update ds80c320 33 mhz ac characteristics. ds80c323: 1. delete data sheet. contents moved to ds80c320/ds80c323. the following represent the key differences between the 05/22/96 and the 10/21/97 version of the ds80c320 data sheet. please review this summary carefully. ds80c320 1. added note to clarify i il specification. ds80c320/ds80c323 42 of 42 2. added note to clarify ac timing conditions. 3. corrected erroneous t qvxl label on figure ?serial port mode 0 timing? to read t qvxh . 4. added note to prevent accidental corruption of watchdog timer count while changing counter length. ds80c323 1. added note to clarify i il specification. 2. remove port 2 from v oh1 specification, add port 3. 3. i oh for v oh3 specification changed from - 3 ma to - 2 ma. 4. added not e to clarify ac timing conditions. |
Price & Availability of DS80C320-QNG
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |